About Leo G. Henry

Leo G. Henry was a Sr. Scientist at ION Systems in Berkeley and before that he was an ESD/TLP Consultant for Barth Electronics Inc. located in Boulder City, Nevada.  Before joining BEI, LeoG worked for AMD as a Member of the Technical Staff (MTS) and as a Product Manager for ORYX Instruments. Over the years, he worked in the areas of fab process development, reliability, device failure analysis and EOS/ESD/Latchup issues.  Leo G. received his B.Sc. and M.Sc.degrees in Physics from the University of the West Indies (U.W.I.).  He attended the three campuses located on the Caribbean Islands of Barbados (Cavehill) and Trinidad (St. Augustine ), respectively.  He also received an M.S. and Ph.D. (1985) degrees in Materials Science and Engineering from the University of California at Berkeley (UCB), CA.

Dr. Henry, who is a member of ASM/EDFAS, IEEE, CSPE and NSPE, has served in several BoD capacities in the Silicon Valley EOS/ESD Society from 1994-2002  including  President (1996-98). For the last seven years, he has been a member of the Silicon Valley EOS/ESD Society Technical Committee for Education, and has tutored at the last six years of the Society’s one day Tutorial called ESDiscovery.  Leo G. has also taught EOS/ESD Failure Signature Analysis and ESD Testing of ICs at the EOS/ESD Symposium (1997-01) and at ASM’s ISTFA (1997 and 1999).  His technical expertise also include latch-up (static and transient) and transmission line pulse testing for ESD robustness.  He has  published many papers on many aspects of ESD.

Leo G Henry's Resume                                                    PDF format     Rich Text Format

Leo G. Henry
39393 Sundale Drive, Fremont, CA 94538
Office: 510-657-5252 Cell: 510-708-5252
leogesd@pacbell.net; emergency email: leogesd@ieee.org

Objectives:

To lead a team or contribute in any of the following ESD related disciplines: ESD Control, ESC/ESD/EMI issues, Ionization issues, EOS/ESD Testing, Latch-up Testing, Failure Analysis and Reliability Engineering

Education:

PhD. 1985: UC Berkeley

Major: Materials Science & Engineering
 

M.S. 1981: UC Berkeley

Major: Materials Science & Engineering
 

B.Sc. 1971: University of the W.I.

Major: Physics with Chemistry minor

Qualifications:
  • Consulted for semiconductor companies in the areas of ESD Basics, ESD Control, and ESD Testing utilizing the EOS/ESD models of HBM, MM, CDM, TLU and TLP.
  • Made presentations to technicians, engineers and managers from major companies in the USA, Europe and ASIA, on ESD Testing including demonstrating ESD test equipment.
  • Wrote specifications for ESD Control and ESD Testing.
  • Managed a team to qualify products through the reliability lab.
  • Taught classes in all aspects of ESD.
  • Analyzed and resolved ionization, ESD/EMI issues for equipment manufacturers in ASIA, Europe and the USA.
  • Active participant in the development of ESD Standards.

ION Systems:

Senior Scientist

2001 - 2002
 
  • Consulted/worked with a team of managers/engineers from several disciplines to solve ESD related problems as they pertain to Ionization, ESD and EMI in the CleanRoom, factory and the field.

Barth Electronics:

ESD/TLP Consulting

2000 - 2001
 
  • Taught and demonstrated the basics of ESD Transmission Line Pulse Testing using the TLP ESD Simulator/Tester at symposiums, conferences, trade shows and IC companies.
  • Partnered with design/product engineers to relate the I-V characteristics shown on the TLP tester to the device performance.

ORYX Corp.

Product Manager, ESD/LUP Products

1998 - 1999
 
  • Interacted with customers, and used the feedback to help improve product development.
  • Partnered with design, software and manufacturing engineers to improve the quality of the ESD Simulators used for both the ICs and the Disk Drive industries.
  • Project managed a team for developing projects on stress testing using the ESD models (HBM, MM, CDM), the transmission line pulser (TLP), and the EOS "models" of static and transient latchup.

Advanced Micro Devices (AMD)

Member of the Technical Staff
Responsibilities:

1983 - 1998
 
  • Electrostatic Discharge (ESD), Electrical Overstress (EOS) and Latchup issues as they relate to device failure analysis, device electrical and physical failure signature analysis.
  • The development of EOS/ESD laboratory simulation for the HBM, MM, CDM and Latchup Models.
  • Knowledge of ESD requirements and the standards for ESD Testing, and ESD control in the workplace.

 

Teaching Experience:

1971- 2002

 
  • Basic TLP for ESD Testing of ICs at the EOS/ESD Symposium, USA.
  • Differentiating between EOS & ESD Testing and Failures in ICs at several symposiums, and conferences and local one-day tutorials.
  • Physics at the University of the West Indies, Trinidad, Caribbean.
  • Teaching Assistant at UC Berkeley
  • Materials Science & Failure Analysis Principles at San Jose State University, CA.

Industry Involvement:
  • ESD Association: 1995-2000, 2002.
  • Silicon Valley EOS/ESD Society: 1994-2002.
  • IDEMA- International Disk drive & Materials Assoc.: 1998-2002.
  • Member of IEEE, ASM, CSPE and NSPE.

Presentations and Publications:

In the areas of Materials science, EOS, ESD, EMI and failure analysis. 23 in refereed conference/symposium/ proceedings, 6 in magazines and 9 in refereed journals.

General skills:

Microsoft Office and the internet. Excellent team, communications and writing skills.

References:

Available upon request.